## Evaluate Window Functions for the Discrete Fourier Transform

The Discrete Fourier Transform (DFT) operates on a finite length time sequence to compute its spectrum. For a continuous signal like a sinewave, you need to capture a segment of the signal in order to perform the DFT. Usually, you also need to apply a window function to the captured signal before taking the DFT [1 - 3]. There are many different window functions and each produces a different approximation of the spectrum. In this post, we’ll present Matlab code that...

## Design a DAC sinx/x Corrector

This post provides a Matlab function that designs linear-phase FIR sinx/x correctors. It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.

A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process. In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses. These are converted by the DAC into contiguous pulses...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## ADC Clock Jitter Model, Part 2 – Random Jitter

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source. What we are calling jitter can also be called time jitter, phase jitter, or phase noise. It’s all the same phenomenon. Typically, we call it jitter when we have a time-domain representation,...

## ADC Clock Jitter Model, Part 1 – Deterministic Jitter

Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock. Jitter on the sample clock causes the sampling instants to vary from the ideal sample time. This transfers the jitter from the sample clock to the input signal.

In this article, I present a Matlab...

## Phase or Frequency Shifter Using a Hilbert Transformer

In this article, we’ll describe how to use a Hilbert transformer to make a phase shifter or frequency shifter. In either case, the input is a real signal and the output is a real signal. We’ll use some simple Matlab code to simulate these systems. After that, we’ll go into a little more detail on Hilbert transformer theory and design.

Phase ShifterA conceptual diagram of a phase shifter is shown in Figure 1, where the bold lines indicate complex...

## Coefficients of Cascaded Discrete-Time Systems

In this article, we’ll show how to compute the coefficients that result when you cascade discrete-time systems. With the coefficients in hand, it’s then easy to compute the time or frequency response. The computation presented here can also be used to find coefficients of mixed discrete-time and continuous-time systems, by using a discrete time model of the continuous-time portion [1].

This article is available in PDF format for...

## Design IIR Filters Using Cascaded Biquads

This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads. We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix. Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc). As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

## Design IIR Highpass Filters

This post is the fourth in a series of tutorials on IIR Butterworth filter design. So far we covered lowpass [1], bandpass [2], and band-reject [3] filters; now we’ll design highpass filters. The general approach, as before, has six steps:

Find the poles of a lowpass analog prototype filter with Ωc = 1 rad/s. Given the -3 dB frequency of the digital highpass filter, find the corresponding frequency of the analog highpass filter (pre-warping). Transform the...## Design IIR Band-Reject Filters

In this post, I show how to design IIR Butterworth band-reject filters, and provide two Matlab functions for band-reject filter synthesis. Earlier posts covered IIR Butterworth lowpass [1] and bandpass [2] filters. Here, the function br_synth1.m designs band-reject filters based on null frequency and upper -3 dB frequency, while br_synth2.m designs them based on lower and upper -3 dB frequencies. I’ll discuss the differences between the two approaches later in this...

## Demonstrating the Periodic Spectrum of a Sampled Signal Using the DFT

One of the basic DSP principles states that a sampled time signal has a periodic spectrum with period equal to the sample rate. The derivation of can be found in textbooks [1,2]. You can also demonstrate this principle numerically using the Discrete Fourier Transform (DFT).

The DFT of the sampled signal x(n) is defined as:

$$X(k)=\sum_{n=0}^{N-1}x(n)e^{-j2\pi kn/N} \qquad (1)$$

Where

X(k) = discrete frequency spectrum of time sequence x(n)

## Peak to Average Power Ratio and CCDF

Peak to Average Power Ratio (PAPR) is often used to characterize digitally modulated signals. One example application is setting the level of the signal in a digital modulator. Knowing PAPR allows setting the average power to a level that is just low enough to minimize clipping.

However, for a random signal, PAPR is a statistical quantity. We have to ask, what is the probability of a given peak power? Then we can decide where to set the average...

## Compute the Frequency Response of a Multistage Decimator

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...

## Canonic Signed Digit (CSD) Representation of Integers

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...

## Digital PLL's -- Part 2

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter. Now let’s look at this PLL in the Z-domain [1, 2]. We will find that the response is characterized by a loop natural frequency ωn and damping coefficient ζ.

Having a Z-domain model of the DPLL will allow us to do three things:

Compute the values of loop filter proportional gain KL and integrator gain KI that give the desired loop natural...## ADC Clock Jitter Model, Part 1 – Deterministic Jitter

Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock. Jitter on the sample clock causes the sampling instants to vary from the ideal sample time. This transfers the jitter from the sample clock to the input signal.

In this article, I present a Matlab...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## Setting Carrier to Noise Ratio in Simulations

When simulating digital receivers, we often want to check performance with added Gaussian noise. In this article, I’ll derive the simple equations for the rms noise level needed to produce a desired carrier to noise ratio (CNR or C/N). I also provide a short Matlab function to generate a noise vector of the desired level for a given signal vector.

Definition of C/NThe Carrier to noise ratio is defined as the ratio of average signal power to noise power for a modulated...

## Find Aliased ADC or DAC Harmonics (with animation)

When a sinewave is applied to a data converter (ADC or DAC), device nonlinearities produce harmonics. If a harmonic frequency is greater than the Nyquist frequency, the harmonic appears as an alias. In this case, it is not at once obvious if a given spur is a harmonic, and if so, its order. In this article, we’ll present Matlab code to simulate the data converter nonlinearities and find the harmonic alias frequencies. Note that Analog Devices has an online tool for...

## Model Signal Impairments at Complex Baseband

In this article, we develop complex-baseband models for several signal impairments: interfering carrier, multipath, phase noise, and Gaussian noise. To provide concrete examples, we’ll apply the impairments to a QAM system. The impairment models are Matlab functions that each use at most seven lines of code. Although our example system is QAM, the models can be used for any complex-baseband signal.

I used a very simple complex-baseband model of a QAM system in my last

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## Canonic Signed Digit (CSD) Representation of Integers

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...

## Matlab Code to Synthesize Multiplierless FIR Filters

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2. For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$. The factor of $2^2$ is then implemented with a shift of 2 bits. This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111. To reduce the number of non-zero...

## Compute the Frequency Response of a Multistage Decimator

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...

## A Simplified Matlab Function for Power Spectral Density

In an earlier post [1], I showed how to compute power spectral density (PSD) of a discrete-time signal using the Matlab function pwelch [2]. Pwelch is a useful function because it gives the correct output, and it has the option to average multiple Discrete Fourier Transforms (DFTs). However, a typical function call has five arguments, and it can be hard to remember how to set them all and how they default.

In this post, I create a simplified PSD function by putting a...

## ADC Clock Jitter Model, Part 2 – Random Jitter

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source. What we are calling jitter can also be called time jitter, phase jitter, or phase noise. It’s all the same phenomenon. Typically, we call it jitter when we have a time-domain representation,...

## Compute Modulation Error Ratio (MER) for QAM

This post defines the Modulation Error Ratio (MER) for QAM signals, and shows how to compute it. As we’ll see, in the absence of impairments other than noise, the MER tracks the signal’s Carrier-to-Noise Ratio (over a limited range). A Matlab script at the end of the PDF version of this post computes MER for a simplified QAM-64 system.

Figure 1 is a simplified block diagram of a QAM system. The transmitter includes a source of QAM symbols, a root-Nyquist...

## ADC Clock Jitter Model, Part 1 – Deterministic Jitter

Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock. Jitter on the sample clock causes the sampling instants to vary from the ideal sample time. This transfers the jitter from the sample clock to the input signal.

In this article, I present a Matlab...

## Modeling a Continuous-Time System with Matlab

Many of us are familiar with modeling a continuous-time system in the frequency domain using its transfer function H(s) or H(jω). However, finding the time response can be challenging, and traditionally involves finding the inverse Laplace transform of H(s). An alternative way to get both time and frequency responses is to transform H(s) to a discrete-time system H(z) using the impulse-invariant transform [1,2]. This method provides an exact match to the continuous-time...

## Coefficients of Cascaded Discrete-Time Systems

In this article, we’ll show how to compute the coefficients that result when you cascade discrete-time systems. With the coefficients in hand, it’s then easy to compute the time or frequency response. The computation presented here can also be used to find coefficients of mixed discrete-time and continuous-time systems, by using a discrete time model of the continuous-time portion [1].

This article is available in PDF format for...